So as we head into the final week before DAC the mad scramble for EDA vendors is underway. Some of them are starting to leak out new products and features. iPad 2 giveaways are in full promotion mode. Gary has released his list..
As I mentioned earlier I am going to DAC as well. I'm going as a consultant and I'll be talking to as many people as I can about Semiconductor IP (#SemIP). I'm looking for inputs on the challenges with integrating IP between groups and companies. I'll be talking about the landscape of IC Design from two perspectives; the IP Provider and the IP Integrator.
The IP Provider (Provider) has the role of providing core analog IP "Functions". This include the traditional analog semiconductor shops. This discipline is analog focused and it's verification environment sits squarely with transistor level simulations (aka spectre/spice).
The role of IP Integrator (Integrator) has the job of integrating the IP from one or many IP Providers. This is your large scale design integration houses. This discipline is digital focused and it's verification environment is gate level functional simulations (aka verilog).
I see lots of challenges in this space. From simple non-functional IP verification checking to data / change-management issues, challenges abound. As an Integrator do you find yourself wishing that you didn't have to spend hours diff-ing IP versions to find the delta? As a Provider what are you doing to verify the liberty model is in sync with the cadence database? Did you update the pin for that PHY in all views & who checks that stuff anyway? Does this sound familiar??
If this sounds familiar - look me up. We need to talk!!
Steven Klass
Email: s_k_l_a_s_s_@7_s_t_a_l_k_s_dot_com
Call or Text: 480.225.1112
Twitter: @rh0dium
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